1. Field of the Invention
The present invention relates generally to multiple bus multiple processor computer systems. In particular, the present invention relates to bus arbitration wherein an indivisible sequence of steps may be preserved upon a device operating on a bus remote from the accessing master even though intervening buses may be released prior to the completion of the indivisible sequence of steps.
2. Art Background
Computer systems frequently make use of bidirectional datapaths, generally known as buses. Buses permit the interconnection of various internal and external peripherals such that the devices may communicate with each other. In larger or more complex computer systems, multiple buses may be used to interconnect a large number of devices, including more than one processor. Devices connected to a bus are generally termed either "master" or "slave", depending on whether the device controls, or is controlled by, another device. In computer systems containing multiple buses, it is necessary to provide a mechanism for determining which device will be permitted to access and control a bus, and which device has priority over another device. The mechanism which controls access by a master to a bus, and thus to slave devices connected to such bus, is generally known as bus arbitration. Arbitration may be accomplished either in hardware, or in software, and enables multiple masters to share the use of a single resource. Bus arbitration is generally accomplished by an arbiter using a hardware implementation, accepting requests for access to a bus from all master devices connected to the bus. The arbiter uses some algorithm, such as fixed priority or round-robin, to determine which requesting master will be granted the next available access cycle to use the particular bus.
Occasionally, it will be necessary for a master to retain ownership and control of a bus for an indivisible number of transactions, thereby preventing other masters from accessing and using the bus, pending completion of the indivisible series of steps. The indivisible sequence of steps or transactions is commonly referred to as an "atomic" or "locked" sequence. Atomic sequences are frequently used to ensure that steps or transactions which must be executed sequentially are in fact executed sequentially, without interruption by other masters accessing the bus. For example, in software semaphores, ownership of the semaphore is obtained by a master reading the contents of a memory location, testing its value, then writing changed contents back into that memory location. Ownership of a semaphore could be nullified if another master were permitted to read from the same memory location and attempt to obtain the same semaphore obtained by the first master asserting the semaphore. Thus, the atomic or locked sequence of steps permits a master asserting ownership of a lock to access and control the register performing the lock function, while precluding access to the register by another master.
Atomic sequences are implemented by a mechanism wherein the arbiter is locked in such a way that a master is not granted immediate access to the bus upon request. Arbitration may be locked in one of two ways. The first is where the arbiter recognizes that an access to the bus will include an atomic sequence, wherein the arbiter does not grant the bus to any other master. The second way to lock arbitration is for the arbiter to grant the bus to the accessing master, but where the current controlling master retains some signal indicating that the bus is busy, and until the controlling master releases such signal, no other accessing master can actually control the bus. In the second case, the master receiving the new bus access grant must wait until the bus busy signal controlled by the current master is extinguished. After the bus busy signal is extinguished, the accessing master can assert control of the bus. In either the first or the second cases, an accessing master must wait until the current controlling master completes its transaction on the bus, and thereafter relinquishes control of the bus and extinguishes the bus busy signal. If the current master transaction is a lengthy one, accessing masters must wait, thereby degrading overall performance of the computer system.
As will be described in more detail in the following paragraphs, the present invention provides methods and circuits to permit locking arbitration such that atomic sequences may be transacted on a remote bus without requiring intermediate or intervening buses to remain locked to a master attempting such atomic sequence, thereby improving system performance. Moreover, the present invention enables such atomic sequences to be transacted upon a remote bus without risk of compromising the atomic sequence. By ensuring that atomic sequences targeted for a remote bus remains secure, coherence of data or signals between masters and slaves operating on different buses is preserved.